1. Field of the Invention
The present invention relates to a multiplexing and transmission apparatus for transporting signals in the Time Division Multiplexing (TDM) regime. In particular, the present invention relates to a very high—speed multiplexing and transmission apparatus beyond 10 Gbit/s.
This application is based on patent application number 2000-180928 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Given the rapid increase of data traffic demand, as can be seen in the well-known situation of the Internet, transmission systems have to provide transmission capacities of the order of Tera bit/s in the near future. To satisfy the huge demand, combined use of Wavelength Division Multiplexing (WDM) and Time Division Multiplexing (TDM) is indispensable because this combination effectively uses fiber bandwidth. Here we focus on TDM technology for the next generation systems.
In the Time Division Multiplexing (TDM) regime, where low speed signals are multiplexed into a high-speed data stream, the traditional approach is to configure a new high-speed digital frame in the transmitter side. FIG. 1 shows an operation example in an Synchronous Digital Hierarchy (SDH) multiplexing apparatus (transmitter). As shown in this figure, frame phase is adjusted when configuring the new high-speed digital frame.
In the receiver side, after detecting the high-speed frame's start position (which is called delimiter) by pattern matching, each channel is identified from its assigned time-position relative to the frame's start position. This operation is shown in FIG. 2 taking the receiver side of the SDH multiplexing apparatus as an example.
The channel identifier of TDM is not manifested on each channel, unlike Wavelength Division Multiplexing (WDM) where the channel identifier is the wavelength of each optical channel, or unlike Asynchronous Transfer Mode (ATM) where the channel identifier is directly written into the VPI (Virtual Path Identifier) field defined in the cell header.
As one example of a TDM application, 10 Gbit/s transmission systems use the Synchronous Digital Hierarchy (SDH) format as shown in FIGS. 1 and 2, more exactly the STM-64 frame specified as the international standard in ITU-T G.707. The receiver detects the start position of the STM-64 frame by special pattern matching at high-speed data rate, and after that each channel is demultiplexed into appropriate tributary port by controlling the demultiplexing circuit: e.g., the byte right after the framing byte is recognized as channel 1, the next byte is for channel 2, and so on. It is common to call the detection of the frame start position as frame synchronization, and, the processing of the frame synchronization for a high-speed serial frame often requires the clock speed to be lowered by serial to parallel conversion. In general, increasing the number of parallel lines results in complex and large-scale circuits. The conventional approach to frame synchronization leads to the following problem.
When the bit rate exceeds 10 Gbit/s, for example 40 Gbit/s, the clock speed is close to the limit of electronic circuits. This complicates the realization of the intelligent processing operations needed such as pattern matching and demultiplexing circuit control required. For a 10 Gbit/s system, frame synchronization is executed at the clock rate of 1.25 GHz or 622 MHz after serial-parallel conversion where the parallel number is usually 8 or 16. Frame synchronization processing in 10 Gbit/s systems is difficult to achieve, even if we use compound semiconductors with large speed margins.
If we use the similar parallel number for frame synchronization in 40 Gbit/s systems, the processing clock rate should be 5 GHz or 2.5 GHz and the intelligent pattern matching processing involved would demand excessive circuit development cost. If we want clock rates of 1.25 GHz or 622 MHz, the parallel number should be 32 or 64, which leads to very complex and large-scale circuits. Moreover, the demultiplexing circuit for a 40 Gbit/s system would consist of several chips, e.g., 1:16 demultiplexer consisting of 1:2 demux, two 1:2 demux and four 1:4 demux. This is because a completely integrated 1:16 demultiplexer is not practical at the clock rate of 40 Gbit/s. The reason to use several chips is that high clock rate devices tend to support only very simple functions, on the other hand, devices suitable for integration operate at low clock rates. Controlling such multi-chip configurations is not practical, because each device has a different interface and timing margin.
For the line rate of 40 Gbit/s, two frame synchronization functions have been standardized: the conventional scheme for SDH in G.707 and that for the Optical channel Transport Unit (OUT)3 (part of the Optical Transport Network (OTN)) in ITU-T G.709. Apparatuses that comply with these international standards is not available today and will be expensive for several years after its introduction.
When we consider even higher data rates, for example 100 Gbit/s, we must accept that electronic circuits will have to be replaced by optical circuits as demultiplexers. In that case, conventional frame synchronization is not feasible, because optical circuits are limited to very simple functions.
A recent trend is to use the SDH interface in various new ways since the cost-effectiveness of hundred-Mbit/s-class SDH interfaces is very attractive to end-users. Thus, an increasing number of manufacturers are configuring their own sub-networks around SDH functionality. They often use the Section Overhead (SOH) for their own purposes and do not worry about complying with standard specifications. Therefore, network carriers that support those sub-networks are required not to terminate the proprietary SOH of users. Therefore, transparency of client overhead is a key requirement for today's transmission equipment.